An oscillator is a circuit that is designed to generate an oscillating waveform. FIG. 1a shows a generic single-ended oscillator circuit that is designed as a “loop” of single ended inverters 101 through 103. Here, note that an odd number of inverters 101 through 103 causes an inherent instability; which, in turn, produces an oscillating waveform 105 at the output node 104 of the oscillator. That is, a “high” at the input of inverter 101 causes a “low” to be presented to inverter 102; which, in turn, causes a “high” to be presented to inverter 103. This causes a “low” to appear at both the output node 104 of the oscillator and the input of inverter 101. Here, in a manner inapposite to that described just above, the “low” presented to inverter 101 will cause a “high” to appear at the output node 104.
As such, the voltage level at output node 104 is inherently unstable which corresponds to the production of an oscillating waveform 105 as drawn in FIG. 1a. The frequency of oscillation of the output waveform 105 can be generically described as 1/(2NPD) where N is the number of inverters in the oscillator (i.e., N=3 in the oscillator embodiment of FIG. 1a) and PD is the propagation delay through any one of inverters 101 through 103 (where each inverter 101 through 103 is assumed to have the same propagation delay PD). FIG. 1b shows a typical single ended inverter that can be used to implement each of inverters 101 through 103 of FIG. 1a. 
In many applications, however, a differential (rather than single-ended) oscillating signal is desired. A differential signal includes a pair of signals (a “+” signal and a “−” signal) where each signal acts as the opposite of the other (i.e., when the “+” signal is “high” the “−” is low and when the “+” signal is “low” the “−” signal is “high”). An example of a differential signal 205 is shown in FIG. 2a by the pair of waveforms observed therein. A differential oscillator circuit can be configured by designing a “loop” of differential inverters 201 through 203 as observed in FIG. 2a. The operation of the differential oscillator of FIG. 2a is much the same as the operation of the operation single ended oscillator of FIG. 1a, except that the differential nature of the inverters 201 through 203 observed therein cause the automatic production of a differential output signal. A typical differential inverter circuit that can be used for each of inverters 201 through 203 is observed in FIG. 2b. 
A problem with the use of a differential inverter circuits like the differential inverter circuit observed in FIG. 2b is that they tend to consumer more power than the single ended inverter structure of FIG. 1b (because of current source 206); and, moreover, exhibit reduced output signal swing as compared to the single ended inverter structure of FIG. 1b (because of the current source-transistor-resistor totem pole structure observed in FIG. 2b). As such, if a design application is sensitive to these drawbacks, a designer may be motivated to attempt a different oscillator circuit approach than that observed in FIGS. 2a and 2b if a differential oscillating signal is desired.
One such approach, referred to as “pseudo-differential”, employs (in the simplest case) the use of a pair of “single ended” channels to effectively create a differential signal (or near differential signal) while still enjoying some of the functional enhancements associated with single ended inverter structures (e.g., reduced power consumption and larger output signal swing). FIG. 3 shows an embodiment of a basic pseudo-differential oscillator circuit. Note that that the oscillator of FIG. 3 is constructed with neighboring pairs 301 through 304 of single ended inverters. A pair of relatively isolated single ended channels (as observed in FIG. 3) is generally not used in practice because the oscillator output might behave as a two separate signals (i.e., the output signal departs from being sufficiently differential (e.g., because the pair of output signals have an unacceptable frequency and/or phase difference).
In order to enhance the differential quality of a pseudo-differential output signal, more sophisticated pseudo-differential oscillators are designed with a series of “delay stage” that each posses internal “cross-coupling”. FIG. 4a shows a pseudo-differential oscillator constructed with four delay stages 401 through 404. FIG. 4b shows an embodiment of a delay stage that may be used for each of the delay stages 401 through 404 of FIG. 4a. Note that the delay stage embodiment of FIG. 4b includes single ended inverter-like structures 406 and 407 in order to: 1) preserve the lower power consumption and high output signal swing functional characteristics that single ended inverter structures provide; and, 2) approximately implement the neighboring “single ended” channel architecture associated with a psuedo-differential oscillator approach.
The delay stage of FIG. 4b also possesses internal “cross-coupling” between its input-to-output paths. Cross coupling is a crossover between + and − signal paths (e.g., from input to output) within a delay stage. Unfortunately, although cross-coupling helps a pseudo-differential oscillator maintain a sufficiently differential output signal, at the same-time, cross-coupling tends to “slow down” the output signal of the oscillator circuit to a frequency of oscillation that is less than that which could have been realized if cross-coupling had not been used. In order to offset this effect “multi-input” delay stages may be used. FIGS. 4a and 4b also correspond to an multi-input delay stage implementation.
The multi-input aspect of delay stages 401 through 404 is utilized, in the pseudo-differential oscillator circuit of FIG. 4a, such that each delay stage provides a direct input not only to its immediately following delay stage but also to its second immediately following delay stage. For example, delay stage 401 not only provides a signal directly to delay stage 402 but also to delay stage 403; delay stage 402 not only provides a signal directly to delay stage 403 but also to delay stage 404;, etc. As alluded to above, using multiple inputs in this manner helps to reduce the frequency loss associated with the cross coupling between signal paths within the delay stages. Thus, at least for field effect transistor (FET) technologies, a pseudo-differential oscillator having multiple input delay stages is a circuit that should produce a sufficiently differential oscillating output signal while exhibiting: 1) higher frequency operation; 2) reduced power consumption; and, 3) larger output signal swing.
Unfortunately, because of the various round trip paths through the oscillator that are introduced by the multiple inputs per delay stage and the instance(s) of cross-coupling within each delay stage, the precise nature of operation for a pseudo differential multi input delay stage oscillator is difficult to characterize or quantify. For example, even though cross coupling helps to prevent an oscillator circuit from reaching a latched state (a condition wherein the inherent instability in the output signal is lost resulting in a constant “DC” output signal rather than an oscillating output-signal) under many circumstances, nevertheless, it remains difficult to characterize or quantify a set of conditions wherein the latched state can arise (i.e., is possible) or cannot arise (i.e., is impossible).
Similarly, even though cross coupling helps to form a sufficiently differential output signal under many circumstances, nevertheless, it remains difficult to characterize or quantify a set of conditions wherein the differential quality of the output signal will be well within an acceptable realm or will depart from being within an acceptable realm (e.g., in an extreme case of unacceptable behavior, referred to as “common mode oscillations, the “+” and “−” signals are duplicates of one another rather than being opposite of one another (i.e., are in-phase rather than out-of-phase).
Given that oscillator circuits are specialized circuits that are often designed to “work” (e.g., meet certain speed, power consumption, signal quality requirements) within a specified range of possible applicable “conditions” (e.g., supply voltage, temperature, manufacturing process tolerances), it behooves a designer to be able to better characterize the nature of operation for a multi input delay stage based pseudo-differential oscillator circuit so that its general behavior as well as its ability to avoid certain detrimental modes of operation (e.g., a latched state, common mode oscillation, etc.) can be specially designed for.